Spacer for semiconductor devices, semiconductor devices and assemblies including the spacer, and methods

ABSTRACT

A semiconductor device that includes at least one nonconfluent spacer layer on at least one surface thereof. The at least one nonconfluent spacer layer at least partially spaces the surface of the semiconductor device apart from another semiconductor device assembled in stacked arrangement therewith. Adjacent stacked semiconductor devices may include abutting nonconfluent spacer layers which together define a distance between opposed surfaces of the semiconductor devices. Each nonconfluent spacer layer includes voids therein that communicate with an exterior periphery of the layer to facilitate the lateral introduction of adhesive or encapsulant material into the layer and between the adjacent, stacked semiconductor devices. Multi-chip modules are also disclosed, as are methods for forming the nonconfluent spacer layers and assembly and packaging methods.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is a divisional of U.S. application Ser. No.09/939,253, filed Aug. 24, 2001, pending.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates generally to multi-chip modulesand, more specifically, to multi-chip modules that include semiconductordevices in stacked arrangement. In particular, the present inventionrelates to multi-chip modules that include at least one semiconductordevice with a spacer predisposed on a surface thereof and anothersemiconductor device in stacked relation thereto and spaced verticallyapart therefrom by way of the predisposed spacer. More particularly, thepredisposed spacer may be printed onto a surface of the at least onesemiconductor device.

[0004] 2. State of the Art

[0005] In order to conserve the amount of surface area, or “realestate,” consumed on a carrier substrate, such as a circuit board, bysemiconductor devices connected thereto, various types ofincreased-density packages have been developed. Among these varioustypes of packages is the so-called “multi-chip module” (MCM). Some typesof multi-chip modules include assemblies of semiconductor devices thatare stacked one on top of another. The amount of space on a carriersubstrate that may be saved by stacking semiconductor devices is readilyapparent-a stack of semiconductor devices consumes roughly the sameamount of real estate on a carrier substrate as a single, horizontallyoriented semiconductor device or semiconductor device package.

[0006] Due to the disparity in processes that are used to form differenttypes of semiconductor devices (e.g., the number and order of variousprocess steps), the incorporation of different types of functionalityinto a single semiconductor device has proven very difficult to actuallyreduce to practice. Even in cases where semiconductor devices that carryout multiple functions can be fabricated, multi-chip modules thatinclude semiconductor devices with differing functions (e.g., memory,processing capabilities, etc.) are often much more desirable since theseparate semiconductor devices may be fabricated and assembled with oneanother much more quickly and cost-effectively (e.g., lower productioncosts due to higher volumes and lower failure rates).

[0007] Multi-chip modules may also contain a number of semiconductordevices that perform the same function, effectively combining thefunctionality of all of the semiconductor devices thereof into a singlepackage.

[0008] An example of a conventional, stacked multi-chip module includesa carrier substrate, a first, larger semiconductor device secured to thecarrier substrate, and a second, smaller semiconductor device positionedover and secured to the first semiconductor device. The secondsemiconductor device does not overlie bond pads of the firstsemiconductor device and, thus, the second semiconductor device does notcover bond wires that electrically connect bond pads of the firstsemiconductor device to corresponding contacts or terminals of thecarrier substrate. Accordingly, the vertical spacing between adjacentsemiconductor devices and, thus, the thickness of the adhesive layer arenot critical. Such a multi-chip module is disclosed and illustrated inU.S. Pat. No. 6,212,767, issued to Tandy on Apr. 10, 2001 (hereinafter“the '767 Patent”). As the sizes of the semiconductor devices of such amulti-chip module must continue to decrease as they are positionedincreasingly higher on the stack, the obtainable heights of suchmulti-chip modules become severely limited.

[0009] Another example of a conventional multi-chip module is describedin U.S. Pat. No. 5,323,060, issued to Fogal et al. on Jun. 21, 1994(hereinafter “the '060 Patent”). The multi-chip module of the '060Patent includes a carrier substrate with semiconductor devices disposedthereon in a stacked arrangement. The individual semiconductor devicesof each multi-chip module may be the same size or different sizes, withupper semiconductor devices being either smaller or larger thanunderlying semiconductor devices. Adjacent semiconductor devices of eachof the multi-chip modules disclosed in the '060 Patent are secured toone another with an adhesive layer, such as preformed, thermoplastictape. The thickness of each adhesive layer exceeds the loop heights ofwire bonds protruding from a semiconductor device upon which thatadhesive layer is to be positioned. Accordingly, the presence of eachadhesive layer prevents the back side of an overlying, uppersemiconductor device from contacting bond wires that protrude from animmediately underlying, lower semiconductor device of the multi-chipmodule. The adhesive layers of the multi-chip modules disclosed in the'060 Patent do not encapsulate or otherwise cover any portion of thebond wires that protrude from any of the lower semiconductor devices.

[0010] A similar but more compact multi-chip module is disclosed in U.S.Pat. Re. No. 36,613, issued to Ball on Mar. 14, 2000 (hereinafter “the'613 Patent”). The multi-chip module of the '613 Patent includes many ofthe same features as those disclosed in the '060 Patent, includingadhesive layers that space adjacent semiconductor devices apart agreater distance than the loop heights of wire bonds protruding from thelower of the adjacent dice. The use of thinner bond wires with low loopprofile wire bonding techniques permits adjacent semiconductor devicesof the multi-chip module disclosed in the '060 Patent to be positionedmore closely to one another than adjacent semiconductor devices of themulti-chip modules disclosed in the '060 Patent. Nonetheless, additionalspace remains between the tops of the bond wires protruding from onesemiconductor device and the back side of the next higher semiconductordevice of such a multi-chip module.

[0011] Conventionally, stacked multi-chip modules that includesemiconductor devices that overlie bond pads of the next, underlyingsemiconductor device include spacers, which may be formed fromdielectric-coated silicon or polyimide film, to space the adjacentsemiconductor devices apart from one another a sufficient distance toprevent bond wires protruding above the lower semiconductor device fromcontacting the back side of the upper semiconductor device. An adhesivematerial typically secures such a spacer between the adjacentsemiconductor devices. When such spacers are used in the fabrication ofmulti-chip modules, each spacer must be properly aligned with and placedupon an active surface of the semiconductor device over which the spaceris to be positioned. These additional assembly processes may be somewhatundesirable for various reasons. For example, positioning of a spacerbetween each pair of adjacent semiconductor devices adds to assemblytime. Further, additional steps in the assembly process increase therisk that semiconductor devices or discrete conductive elements may bedamaged. In addition, the use of preformed spacers may undesirably addto the cost of a multichip module.

[0012] The vertical distance that adjacent semiconductor devices of astacked type multi-chip module are spaced apart from one another may bereduced by arranging the immediately underlying semiconductor devicessuch that upper semiconductor devices are not positioned over bond padsof immediately underlying semiconductor devices or bond wires protrudingtherefrom. The vertical spacing of adjacent semiconductor devices insuch an assembly is not critical and may be a distance that is less thanthe loop heights of the wire bonds that protrude above the activesurface of the lower semiconductor device. U.S. Pat. No. 6,051,886,issued to Fogal et al. on Apr. 18, 2000 (hereinafter “the '886 Patent”)discloses such a multi-chip module. According to the '886 Patent, wirebonding is not conducted until all of the semiconductor devices of sucha multi-chip module have been assembled with one another and with theunderlying carrier substrate. The semiconductor devices of themulti-chip modules disclosed in the '886 Patent must include bond padsthat are arranged on opposite peripheral edges. Semiconductor deviceswith bond pads positioned adjacent the entire peripheries thereof couldnot be used in the multi-chip modules of the '886 Patent. This is aparticularly undesirable limitation due to the ever-increasing featuredensity of state-of-the-art semiconductor devices, which is oftenaccompanied by a consequent need for an ever-increasing number of bondpads on semiconductor devices.

[0013] In view of the foregoing, it appears that semiconductor devicesincluding stacking spacers formed directly on at least one side thereofwould be useful, as would methods for forming such assemblies.

BRIEF SUMMARY OF THE INVENTION

[0014] The present invention includes a semiconductor device for use ina stacked assembly of semiconductor devices. As used herein, the term“semiconductor device” includes, but is not limited to, semiconductordice, as well as full or partial wafers or other semiconductorsubstrates that include pluralities of semiconductor devices fabricatedthereon. The semiconductor device includes at least one spacer layerthat has been disposed on portions of a surface thereof to facilitatestacking of the semiconductor device with other semiconductor devices. Aspacer layer may be disposed on a single surface of the semiconductordevice or on both surfaces thereof.

[0015] A spacer layer incorporating teachings of the present inventionmay include a plurality of laterally discrete spacers, a somewhatcontiguous layer with voids formed therein that communicate with anexterior periphery of the spacer layer, or any other nonconfluentconfiguration that facilitates the lateral flow of adhesive materialthrough the spacer layer and between the adjacent semiconductor devicesseparated thereby. As used herein, the term “nonconfluent” applies tolayers that include voids therein, such as, for example only, layersthat include laterally discrete members, as well as layers that includeinternalized or externally communicating voids that extend completely orpartially therethrough and layers that are not otherwise completelysolid throughout the entire lateral surface areas thereof.

[0016] By way of example only, each spacer layer may be formed from adielectric material. Dielectric materials such as polymers (e.g.,epoxies, polyimides, or the like) may be used to form each spacer layer.The polymer may be a fully or partially cured or hardened thermosetresin, a UV-curable material, a thermoplastic resin, a silicone, asilicone-carbon resin, a polyimide, a polyurethane, a parylene, or thelike. When a polymer is used, a spacer layer may be formed on a surfaceof a semiconductor device by screen printing, jet printing, needledispensing, or other suitable processes. Curing of or otherwisehardening the polymer may then be effected by suitable processes,depending upon the type of polymer employed. Alternatively, each spacerlayer may comprise a preformed layer that is adhered to a surface of thesemiconductor device.

[0017] As an alternative, dielectric materials that are typicallyemployed in semiconductor device fabricating processes, such as glass,undoped silicon oxides, silicon nitrides, and silicon oxynitrides, maybe used to form the spacer layer. In the event that such materials areused, a material layer may be formed by suitable processes (e.g.,spin-on glass (SOG), chemical vapor deposition (CVD) processes, etc.)then patterned (e.g., by mask and etch processes) to remove material atselected regions of the layer.

[0018] If a spacer layer is formed from a conductive or semiconductivematerial, the spacer layer may be fabricated by deposition (e.g., CVD,physical vapor deposition (PVD) (e.g., sputtering), etc.) and patterningprocesses that are suitable for the particular material used. A spacerlayer that is formed from conductive or semiconductive material ispreferably electrically isolated from structures that are located orwill be positioned adjacent thereto, such as the active surface or backside of a semiconductor device. By way of example, the protective glasslayer that is typically formed on the active surfaces of semiconductordevices may serve to electrically isolate the active surface of asemiconductor device from a spacer layer that includes conductive orsemiconductive material. As another example, a conductive orsemiconductive spacer layer may be coated with a dielectric material,such as an electrically nonconductive oxide of the conductive orsemiconductive material from which the spacer layer is formed. The backside or active surface of an adjacent semiconductor device may beelectrically isolated from a conductive or semiconductive spacer layerby way of a dielectric coating thereon. Such a dielectric coating may besubstantially confluent or may cover only portions of the back side thatare to be located adjacent to the conductive or semiconductive materialof the spacer layer.

[0019] Each spacer layer may have a thickness that will, either alone orin combination with the thickness of another, adjacent spacer layer ofanother semiconductor device, prevent portions of discrete conductiveelements that protrude above a surface of one or both of the adjacentsemiconductor devices from contacting the other of the adjacentsemiconductor devices.

[0020] Formation or disposal of the spacer layer may be effected oneither individual semiconductor devices, simultaneously on groups ofindividual semiconductor devices, or on semiconductor devices that haveyet to be singulated from a large-scale substrate, such as a wafer orportion thereof.

[0021] The spacer layer is preferably disposed on the semiconductordevice prior to assembly thereof with other components. Thus,semiconductor devices on which spacer layers have been formed ordisposed may be tested prior to assembly or packaging thereof with othercomponents. The effects of forming or disposing the spacer layer on theoperability or reliability of a semiconductor device may, therefore, beevaluated prior to assembly or packaging of the semiconductor devicewith other components. Consequently, semiconductor devices that aredamaged or rendered inoperable by formation or disposal of the spacerlayer thereon may be discovered and discarded prior to assembly orpackaging thereof.

[0022] A stacked assembly incorporating teachings of the presentinvention includes a first semiconductor device, a second semiconductordevice, a spacer layer between the first and second semiconductordevices, and discrete conductive elements that are connected to bondpads of and protrude from a surface of one of the semiconductor devices.

[0023] The spacer layer may secure the first and second semiconductordevices to one another. By way of example, an adhesive material may beapplied to all or part of an exposed surface of the spacer layer priorto assembling the first and second semiconductor devices with eachother. Alternatively, the spacer layer may comprise an uncured orpartially cured material that may be adhered to an adjacent spacer layeror a surface of a semiconductor device upon contacting the same or uponat least partially curing the material of the spacer layer, securing thefirst and second semiconductor devices to one another.

[0024] Of course, such an assembly may include more than twosemiconductor devices in stacked arrangement with one another.

[0025] One of the semiconductor devices of a stacked assembly may besecured to or otherwise associated with a substrate. Exemplarysubstrates include, but are not limited to, circuit boards, interposers,other semiconductor devices, and leads. Discrete conductive elements,such as bond wires, tape-automated bond (TAB) elements comprisingconductive traces on a dielectric film, leads, or the like, mayelectrically connect bond pads of one or more of the semiconductordevices of such a stacked assembly to corresponding contact areas of asubstrate.

[0026] An assembly incorporating teachings of the present invention maybe part of a package and, thus, include a protective encapsulantcovering at least portions of the semiconductor devices, the discreteconductive elements, and regions of a substrate that are locatedadjacent to at least one of the semiconductor devices. Such a packagemay also include external connective elements that communicate withcorresponding contact areas of the substrate and/or bond pads of one ormore of the stacked semiconductor devices.

[0027] In another aspect of the present invention, a spacer layerincorporating teachings of the present invention may be designed byconfiguring regions that each have a thickness that will, either aloneor in combination with an adjacent spacer layer, separate twosemiconductor devices apart from one another a set distance. By way ofexample only, the set distance may be sufficient to prevent discreteconductive elements protruding above the surface of one or both of thesemiconductor devices and located between the semiconductor devices fromcontacting a surface of the other adjacent semiconductor device.Alternatively, the discrete conductive elements protruding above asurface of one of the adjacent, stacked semiconductor devices maycontact a surface of the other, adjacent semiconductor device if atleast contacting portions of either or both of the discrete conductiveelements and semiconductor device surfaces are electrically isolatedfrom one another. A method for designing a spacer layer in accordancewith the present invention may also include configuring solid regionsand voids that will facilitate the flow of an underfill or encapsulantmaterial therethrough while reducing or eliminating the incidence ofvoids in the underfill or encapsulant material.

[0028] The present invention also includes methods for forming spacerlayers, methods for forming semiconductor devices that include thespacer layers, methods for assembling such a semiconductor device withone or more other semiconductor devices, and-methods for packaging suchassemblies.

[0029] Other features and advantages of the present invention willbecome apparent to those of ordinary skill in the art throughconsideration of the ensuing description, the accompanying drawings, andthe appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In the drawings, which illustrate exemplary embodiments ofvarious aspects of the present invention:

[0031]FIG. 1 is a perspective view of an exemplary embodiment of asemiconductor device incorporating teachings of the present invention,which semiconductor device includes a spacer layer on an active surfacethereof;

[0032]FIG. 2 is a cross-section taken along line 2-2 of FIG. 1;

[0033]FIG. 3 is a perspective view illustrating another, invertedsemiconductor device according to the present invention, which includesa spacer layer on a back side thereof;

[0034]FIG. 4 is a side view that depicts a semiconductor device withspacer layers on both an active surface and a back side thereof;

[0035]FIG. 5 schematically depicts the use of screen printing techniquesto form the spacers of a spacer layer on a semiconductor device;

[0036] FIGS. 6A-6D are schematic representations of the use ofsemiconductor device fabrication processes to form the spacers of aspacer layer on a semiconductor device;

[0037] FIGS. 7A-7D schematically illustrate formation of the spacers ofa spacer layer on a semiconductor device by way of stereolithography;

[0038]FIG. 8 schematically depicts the formation of spacers by way of adispensing process;

[0039]FIG. 9 is a cross-sectional representation of a stacked assemblythat includes the semiconductor devices of FIGS. 1 and 2;

[0040]FIGS. 9A and 9B schematically represent an embodiment ofsemiconductor device to be used in a stacked assembly and that includesspacers formed over portions of discrete conductive elements thatprotrude over the active surface thereof;

[0041]FIG. 9C is a cross-sectional representation of another embodimentof stacked semiconductor device assembly that includes the semiconductordevice of FIGS. 1 and 2;

[0042]FIG. 10 is a side view of another stacked assembly, which includesa semiconductor device of the type shown in FIGS. 1 and 2 with asemiconductor device of the type illustrated in FIG. 3 stacked thereon;

[0043]FIG. 11 is a side view of a stacked assembly including more thantwo semiconductor devices in stacked arrangement; and

[0044]FIG. 12 is a cross-sectional representation of a package includingan assembly of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0045] With reference to FIGS. 1 and 2, an exemplary embodiment of asemiconductor device 10 is illustrated. Semiconductor device 10 includesa spacer layer 20 on an active surface 12 thereof.

[0046] Spacer layer 20 is positioned on active surface 12 or configuredsuch that bond pads 16 of semiconductor device 10 are exposed beyond anouter periphery of spacer layer 20 or are otherwise accessible toequipment for forming or positioning discrete conductive elements (e.g.,a wire bonding capillary, thermocompression bonding equipment, etc.).

[0047] As depicted, spacer layer 20 includes a plurality of discrete,laterally spaced apart solid regions, which are referred to herein asspacers 22, and voids 24 that are located between adjacent spacers 22.Although spacers 22 are depicted in FIGS. 1 and 2 as being laterallyoffset from bond pads 16, if formed following the connection of discreteconductive elements 18 (see, e.g., FIG. 10) to bond pads 16, anysuitable embodiment of spacer 22 incorporating teachings of the presentinvention may be formed over bond pads 16, as well as the portions ofdiscrete conductive elements 18 that are proximate thereto. Due to thepresence of voids 24 in spacer layer 20, spacer layer 20 covers onlyportions of active surface 12. Voids 24 are configured and arranged toreceive an underfill or encapsulant material, which may, at least inpart, secure semiconductor device 10 to another at least partiallysuperimposed semiconductor device 110 (FIG. 9). Other nonconfluentconfigurations of spacer layers that are configured to permit anadhesive material to flow laterally thereinto and thereby substantiallyfill voids in the spacer layer are also within the scope of the presentinvention.

[0048] Spacers 22 and voids 24 of spacer layer 20 may be arrangedrandomly or in a pattern. The configurations of spacers 22 and voids 24may facilitate the introduction of an underfill or encapsulant materialinto voids 24 while reducing or eliminating the incidence of void orbubble formation in the underfill or encapsulant material.

[0049] Spacers 22 may be substantially identically configured or havedifferent configurations. By way of example only, spacers 22 may havesubstantially planar upper surfaces and cross-sectional shapes takenalong the length thereof including, but not limited to, round shapes(e.g., circular, ovals, ellipsoids, etc.), polygonal shapes (e.g.,triangular, square, diamond-shaped, rectangular, hexagonal, octagonal,etc.) (see FIG. 4), crosses, elongate members which may be straight,bent, or curved, and other shapes. Alternatively, the upper surfaces ofspacers 22 may be nonplanar, such as cones, pyramids, the depicteddomes, or other suitable shapes. Spacers 22 may comprise solid or atleast partially hollow members.

[0050]FIG. 3 illustrates another embodiment of semiconductor device 10′,which includes a spacer layer 20 on a back side 14′ thereof. Spacerlayer 20 may include any combination of features described above withreference to FIGS. 1 and 2.

[0051] Another embodiment of semiconductor device 10″ is shown in FIG.4. Semiconductor device 10″ includes spacer layers 20 on both an activesurface 12″ and a back side 14″ thereof.

[0052] FIGS. 5-8 illustrate exemplary methods by which spacer layers 20and their spacers 22 may be fabricated.

[0053]FIG. 5 schematically depicts the use of a screen printing processin which a spacer layer 20 is formed on a semiconductor device 10′″,shown in the form of a wafer including a plurality of devices fabricatedthereon. A screen 210 of a known type with a spacer pattern 220 thereinis positioned over and aligned with semiconductor device 10′″. Spacerpattern 220 includes apertures 222 through which regions of an activesurface 12′″ of semiconductor device 10′″ are exposed. A quantity of asuitable spacer material 215 is then placed on screen 210 and spreadthereacross, causing some of spacer material 215 to fill apertures 222and adhere to active surface 12″′. Screen 210 may then be removed fromsemiconductor device 10″′, with spacer material 215 that remains onactive surface 12′″ forming spacers 22 of spacer layer 20. The materialof spacers 22 may be cured or otherwise hardened by a process (e.g.,thermally, by irradiation, by cooling, etc.) or combination of processesthat is suitable for the particular type of spacer material 215employed.

[0054] A method in which conventional semiconductor device fabricationprocesses are used to form spacers 22 of spacer layer 20 is illustratedin FIGS. 6A-6D. In FIG. 6A, a layer 220′ of a material suitable for useas spacers 22 (FIG. 6D) is formed over an active surface 12 of asemiconductor device 10. Known processes (e.g., spreading, exposure, anddeveloping of a photoimageable polymer) may then be used to form a mask230 over layer 220′. Solid regions 231 of mask 230 cover portions oflayer 220′ that will subsequently form spacers 22 of spacer layer 20(FIG. 6D), while other regions of layer 220′, which are to be removed,are exposed through apertures 232 of mask 230. Semiconductor device 10and mask 230 may then be exposed to an etchant that will remove thematerial of layer 220′ in regions thereof that are exposed throughapertures 232, as depicted in FIG. 6C. Upon removing the desiredportions of layer 220′, spacers 22 of spacer layer 20 are formed. Mask230 may be removed from spacer layer 20 by known processes (e.g., use ofa suitable resist strip when mask 230 comprises a photomask).

[0055] FIGS. 7A-7D schematically depict an exemplary stereolithographyprocess for fabricating spacer layer 20 (FIG. 7D) on an active surface12 of a semiconductor device 10. As shown in FIG. 7A, active surface 12of semiconductor device 10 may be submerged beneath a quantity ofunconsolidated material 213″ (e.g., a liquid photoimageable polymer),which forms a layer 215″ over active surface 12. In FIG. 7B, selectedregions of layer 215″ are at least partially consolidated, as known inthe art (e.g., by exposure of a liquid photoimageable polymer to curingradiation, such as a laser beam 235). The at least partiallyconsolidated portions of layer 215″ form sublayers 22 a of spacers 22 ofspacer layer shown in FIGS. 7C and 7D, one or more times to form aplurality of at least partially superimposed, contiguous, mutuallyadhered sublayers 22 a, 22 b, etc. of spacers 22. As depicted in FIG.7D, each spacer 22 includes two sublayers 22 a, 22 b, although stereolithographically fabricated spacers 22 having single layers or othernumbers of sublayers are also within the scope of the present invention.

[0056] As another alternative, illustrated in FIG. 8, spacers 22 may beformed by dispensing small, laterally discrete quantities of a spacermaterial, such as a polymer (e.g, an epoxy, thermoplastic polymer,etc.), directly onto an active surface 12 of a semiconductor device 10that is singulated or part of a wafer, partial wafer, or otherlarge-scale fabrication substrate. By way of example, such dispensingmay be effected by way of an appropriately sized dispensing needle 300.

[0057] Of course, the process by which spacers 22 of spacer layers 20are formed depends at least in part upon the particular materials usedto form spacers 22.

[0058] Referring now to FIG. 9, an assembly 30 is depicted that includesa substrate 40, a first semiconductor device 10, and a secondsemiconductor device 110 stacked on first semiconductor device 10.Discrete conductive elements 18 electrically connect bond pads 16 offirst semiconductor device 10 to corresponding contact areas 46 ofsubstrate 40. Second semiconductor device 110 may overlie at least somebond pads 16 of first semiconductor device 10, as well as any discreteconductive elements 18 extending therefrom. First semiconductor device10 and second semiconductor device 110 are separated from one another byway of spacers 22 located therebetween.

[0059] While substrate 40 is depicted as an interposer of which contactareas 46 are bond pads located on a top side 44 thereof, other types ofsubstrates are also within the scope of the present invention,including, without limitation, circuit boards, other semiconductordevices, and leads.

[0060] In the illustrated example, back side 14 of first semiconductordevice 10 is secured to substrate 40 by way of a suitable adhesivematerial 15, such as a thermoplastic resin, a silicon-filledthermoplastic resin, a thermoset resin, an epoxy, a silicone, asilcone-carbon resin, a polyimide, a polyurethane, or a parylene. Ofcourse, first semiconductor device 10 may be secured to or otherwiseassociated with a substrate in a different manner, depending upon theparticular type of substrate employed. By way of example only, leads mayextend partially over and be secured to active surface 12 of firstsemiconductor device 10. Such leads may extend over corresponding bondpads 16 and be secured thereto directly (e.g., by thermocompressionbonds) or by way of conductive joints (e.g., balls, bumps, pillars,columns; or other structures of a metal or metal alloy, such as solder,a conductive epoxy, a conductor-filled epoxy, or a z-axis conductiveelastomer).Alternatively, discrete conductive elements, such as bondwires or TAB elements may be positioned or formed between each lead andits corresponding bond pad 16 to electrically connect the same.

[0061] The heights of spacers 22 may be greater than the distancediscrete conductive elements 18 protrude above active surface 12 offirst semiconductor device 10, thereby preventing discrete conductiveelements 18 from electrically shorting on a back side 114 of theoverlying second semiconductor device 110.

[0062] Alternatively, the heights of spacers 22 may be about the same asor even smaller than the distances discrete conductive elements 18protrude above active surface 12, so long as the heights of spacers 22and the combined strengths of discrete conductive elements 18 over whichsecond semiconductor device 110 is positioned prevent discreteconductive elements 18 from being damaged (e.g., by being bent, kinked,or otherwise deformed) or from collapsing onto one another. If theheights of spacers 22 are less than the distance discrete conductiveelements 18 protrude above active surface 12, it is preferred thatportions of discrete conductive elements 18 and back side 114 that maycontact one another be electrically isolated from each other. By way ofexample, at least portions of discrete conductive elements 18 mayinclude a dielectric coating 19 thereon. Alternatively, or in addition,all or part of back side 114 may include a dielectric coating 116.Suitable dielectric materials for both dielectric coating 19 anddielectric coating 116 include, but are not limited to, nonconductivepolymers, glass, silicon oxide, silicon nitride, and silicon oxynitride,as well as nonconductive oxides of the respective discrete conductiveelement 18 or semiconductor device 110 material.

[0063] An adhesive material 115, such as a thermoset resin, a UV-curablematerial, a thermoplastic resin, a silicone, a silicone-carbon resin, apolyimide, a polyurethane, a parylene, or the like, may be locatedbetween active surface 12 of first semiconductor device 10 and back side114 of second semiconductor device 110, securing first and secondsemiconductor devices 10 and 110 to one another.

[0064] In FIGS. 9A and 9B, a partial assembly 30′″ is shown thatincludes a semiconductor device 10′″ positioned over and secured to asubstrate 40. Discrete conductive elements 18, such as bond wires,electrically connect bond pads 16 of semiconductor device 10′″ tocorresponding contact areas 46 of substrate 40. Spacers 22′″ are formedover portions of discrete conductive elements 18 and may support and/orprotect discrete conductive elements 18 as a second semiconductor device(not shown) is subsequently assembled thereover. While each spacer 22′″is depicted in FIG. 9B as an elongate member that encapsulates portionsof a plurality of discrete conductive elements 18, other configurationsof spacers that encapsulate discrete conductive elements 18 are alsowithin the scope of the present invention, including, withoutlimitation, smaller spacers that encapsulate portions of single discreteconductive elements 18.

[0065]FIG. 9C depicts an assembly 130 that includes semiconductordevices 10, 110, as well as spacers 22 and adhesive material 115therebetween, that are similar to those of assembly 30 depicted in FIG.9. Assembly 130 differs from assembly 30 in that substrate 140 comprisesleads 142. As depicted, leads 142 are of a leads-over-chip (LOC)configuration and, thus, extend partially over and are secured to anactive surface 12 of first semiconductor device 10. In addition, leads142 are positioned at least partially over and bonded to correspondingbond pads 16 of first semiconductor device 10. By way of example only,leads 142 may be bonded to corresponding bond pads 16 by way ofthermocompression bonds or by the use of a conductive adhesive material,such as solder, another metal or metal alloy, conductive orconductor-filled epoxy, an anisotropically conductive elastomer, or thelike, between leads 142 and bond pads 16. Alternatively, LOC type leads142 may communicate with corresponding bond pads 16 by way of discreteconductive elements (e.g., bond wires, TAB elements, etc.). Othervariations of the assemblies depicted herein may include substrates thatcomprise other types of leads, circuit boards, an additionalsemiconductor device, or the like.

[0066] In FIG. 10, another embodiment of assembly 30′ includes a firstsemiconductor device 10 with a second semiconductor device 10′ stackedthereon. As first semiconductor device 10 includes a spacer layer 20 onactive surface 12 thereof and second semiconductor device 10′ includes aspacer layer 20 on a back side 14′ thereof (see also FIG. 3), spacerlayers 20 are positioned adjacent to one another. At least some spacers22 of the adjacent spacer layers 20 abut each other, with the combinedheights of abutting spacers 22 defining the distance between firstsemiconductor device 10 and second semiconductor device 10′.

[0067] An assembly incorporating teachings of the present invention mayinclude more than two semiconductor devices in stacked arrangement. FIG.11 illustrates such an assembly 30″, which includes a substrate 40 andthree semiconductor devices 10, 110 in stacked arrangement thereon.

[0068] Referring again to FIG. 9, an exemplary process for formingassembly 30 includes securing a first semiconductor device 10 to asubstrate 40. As depicted, an adhesive material 15 is used, althoughother known methods for securing semiconductor devices to substrates arealso within the scope of the present invention. Known processes may beused to form or position discrete conductive elements 18, such as TABelements, thermocompression bonded leads, the depicted bond wires, orthe like, between bond pads 16 of semiconductor device 10 andcorresponding contact areas 46 of substrate 40. Spacers 22 may be formedon regions of active surface 12 of semiconductor device 10 by knownprocesses, such as those described previously herein with reference toFIGS. 5-8. The formation of spacers 22 may be effected before or aftersemiconductor device 10 is secured to substrate 40, as well as before orafter the formation of discrete conductive elements 18. A secondsemiconductor device 110 is positioned over spacers 22, with a back side114 thereof resting against spacers 22.

[0069] Optionally, a suitable adhesive material 115, such as a knownunderfill material, may be introduced into voids 24 of spacer layer 20,between active surface 12 of first semiconductor device 10 and back side114 of second semiconductor device 110. When spacers 22 at leastpartially encapsulate discrete conductive elements 18, as depicted inFIG. 10, spacers 22 may prevent discrete conductive elements 18 frombeing collapsed onto one another, bent, kinked, or otherwise distortedor damaged during the introduction of adhesive material 115 betweenfirst and second semiconductor devices 10 and 110. One or more knownprocesses may be used to at least partially cure or otherwise hardenadhesive material 115. Spacers 22 that at least partially encapsulatediscrete conductive elements 18 may also electrically isolate discreteconductive elements from the back side 114 of an adjacent semiconductordevice 110.

[0070] Alternatively, a relatively high viscosity adhesive material 115may be applied to a surface of one or both of first and secondsemiconductor devices 10 and 110 prior to assembly thereof with oneanother. Then, when first and second semiconductor devices 10 and 110are assembled, adhesive material 115 fills voids 24 of spacer layer 20and contacts opposed surfaces (e.g., active surface 12 and back side114, respectively) of first semiconductor device 10 and secondsemiconductor device 110. Following the assembly of first semiconductordevice 10 and second semiconductor device 110, one or moreknown.processes may be used to at least partially cure or otherwiseharden adhesive material 115.

[0071] Turning now to FIG. 12, a package 50 incorporating teachings ofthe present invention may include any assembly (e.g., assemblies 30,30′, 30″) according to the present invention. As illustrated, package 50includes assembly 30, as well as an encapsulant 52 substantially fillingvoids 24 in spacer layer 20 and surrounding semiconductor devices 10 and110, discrete conductive elements 18, and portions of substrate 40 thatare located adjacent to semiconductor device 10. Alternatively,encapsulant 52 may be formed separately from a layer of adhesivematerial 115 (see, e.g., FIG. 9) between first semiconductor device 10and second semiconductor device 110.

[0072] While encapsulant 52 is depicted as being formed by transfermolding processes or by pot molding processes and, thus, fromappropriate compounds (e.g., a silicon-filled thermoplastic resin fortransfer molding or an epoxy for pot molding), other encapsulationtechniques, such as glob top processes, and appropriate materials mayalso be used to form encapsulant 52. Although encapsulant 52 may beformed separately from the layer of adhesive material 115 between firstand second semiconductor devices 10 and 110, the same or similarmaterials may be used as adhesive material 115 and to form encapsulant52. Likewise, adhesive material 115 and/or the material of encapsulant52 may comprise the same or a similar material to that from whichspacers 22 are formed. Use of the same or similar materials for theseelements may optimized adhesion and provide for a matched coefficient ofthermal expansion (CTE).

[0073] Package 50 may also include external connective elements 54electrically coupled to contact areas 46 by vias and/or conductivetraces (not shown) carried by substrate 40, as known in the art.External connective elements 54 may, by way of example only, compriseconductive plug-in type connectors, pin connectors, conductive orconductor-filled epoxy pillars, an anisotropically conductive adhesive,the depicted conductive bumps, or any other conductive structures thatare suitable for interconnecting assembly 30 with other, externalelectronic components.

[0074] Although the foregoing description contains many specifics, theseshould not be construed as limiting the scope of the present invention,but merely as providing illustrations of some exemplary embodiments.Similarly, other embodiments of the invention may be devised which donot depart from the spirit or scope of the present invention. Featuresfrom different embodiments may be employed in combination. The scope ofthe invention is, therefore, indicated and limited only by the appendedclaims and their legal equivalents, rather than by the foregoingdescription. All additions, deletions, and modifications to theinvention, as disclosed herein, which fall within the meaning and scopeof the claims are to be embraced thereby.

What is claimed is:
 1. A method for preparing a semiconductor device tobe used in a multi-chip module, comprising: providing at least onesemiconductor device; and forming at least one nonconfluent spacer layeron at least one surface of said at least one semiconductor device. 2.The method of claim 1, wherein said forming comprises formingnonconfluent spacer layers on both surfaces of said at least onesemiconductor device.
 3. The method of claim 1, wherein said formingcomprises screen printing.
 4. The method of claim 1, wherein saidforming comprises: forming a material layer on said at least onesurface; and patterning said material layer.
 5. The method of claim 4,wherein said forming said material layer comprises depositing saidmaterial layer.
 6. The method of claim 4, wherein said patterningcomprises: forming a mask over said material layer; and removingportions of said material layer exposed through said mask.
 7. The methodof claim 1, wherein said forming comprises stereolithographicallyforming said at least one nonconfluent spacer layer.
 8. The method ofclaim 7, wherein said stereolithographically forming comprises: forminga layer comprising unconsolidated material over said at least onesurface; and at least partially consolidating selected portions of saidlayer.
 9. The method of claim 8, further comprising: forming at leastone additional layer comprising unconsolidated material over said layer;and at least partially consolidating selected portions of said at leastone additional layer, said at least partially consolidated portions ofsaid another layer being at least partially superimposed over,contiguous with, and adhered to said at least partially consolidatedportions of said layer.
 10. The method of claim 9, further comprising:repeating said forming and said at least partially consolidating atleast once.
 11. A method for designing a semiconductor device to be usedin a stacked multi-chip module, comprising: configuring at least onenonconfluent spacer layer to be positioned on at least one surface ofthe semiconductor device.
 12. The method of claim 11, wherein saidconfiguring comprises configuring said at least one nonconfluent spacerlayer with at least one void to facilitate lateral introduction ofadhesive material through said at least one nonconfluent spacer layeronto said at least one surface of the semiconductor device.
 13. Themethod of claim 11, wherein said configuring comprises configuring saidat least one nonconfluent spacer layer to have a thickness that exceedsa distance at least one discrete conductive element will protrude abovea surface of at least one of the semiconductor device and another,adjacent semiconductor device of the multi-chip module.
 14. The methodof claim 11, wherein said configuring comprises configuring said atleast one nonconfluent spacer layer to have a thickness that is aboutthe same as or less than a distance at least one discrete conductiveelement will protrude above a surface of at least one of thesemiconductor device and another, adjacent semiconductor device of themulti-chip module.
 15. The method of claim 11, wherein said configuringcomprises configuring said at least one nonconfluent spacer layer toinclude a plurality of laterally discrete spacers.
 16. The method ofclaim 11, wherein said configuring comprises configuring said at leastone nonconfluent spacer layer to be positioned adjacent another spacerlayer, said at least one nonconfluent spacer layer and said anotherspacer layer together defining a distance the semiconductor device is tobe spaced apart from another, adjacent semiconductor device of themulti-chip module.
 17. A method for forming a stacked assembly ofsemiconductor devices, comprising: providing a first semiconductordevice; applying a nonconfluent spacer layer to at least one surface ofsaid first semiconductor device; and positioning a second semiconductordevice in stacked arrangement relative to said first semiconductordevice, said nonconfluent spacer layer at least partially spacing saidfirst and second semiconductor devices apart from one another.
 18. Themethod of claim 17, further comprising: securing said firstsemiconductor device and a substrate to one another.
 19. The method ofclaim 18, wherein said securing comprises securing a back side of saidfirst semiconductor device to said substrate.
 20. The method of claim18, wherein said securing comprises securing said substrate to portionsof an active surface of said first semiconductor device.
 21. The methodof claim 18, further comprising: electrically connecting at least onebond pad of said first semiconductor device to a corresponding contactarea of said substrate.
 22. The method of claim 21, wherein saidelectrically connecting comprises: positioning or forming a discreteconductive element between said at least one bond pad and saidcorresponding contact area.
 23. The method of claim 21, wherein saidelectrically connecting comprises placing a lead at least partially oversaid at least one bond pad.
 24. The method of claim 18, wherein saidapplying is effected before said securing.
 25. The method of claim 18,wherein said applying is effected after said securing.
 26. The method ofclaim 21, wherein said applying is effected after said electricallyconnecting.
 27. The method of claim 17, further comprising: applyinganother nonconfluent spacer layer to at least one surface of said secondsemiconductor device.
 28. The method of claim 27, wherein, upon saidpositioning, said nonconfluent spacer layer and said anothernonconfluent spacer layer are positioned against one another.
 29. Themethod of claim 17, wherein, upon said positioning, said nonconfluentspacer layer adheres said first and second semiconductor devices to oneanother.
 30. The method of claim 17, further comprising: laterallyintroducing adhesive material into voids in said nonconfluent spacerlayer and between said first and second semiconductor devices.
 31. Themethod of claim 30, further comprising at least one of at leastpartially curing and at least partially hardening said adhesivematerial.
 32. The method of claim 21, further comprising: electricallyconnecting at least one bond pad of said second semiconductor device toanother corresponding contact area of said substrate.
 33. The method ofclaim 32, further comprising: encapsulating at least portions of saidfirst semiconductor device, said second semiconductor device, and saidsubstrate.
 34. The method of claim 33, wherein said encapsulatingcomprises forming a molded encapsulant.
 35. The method of claim 33,wherein said encapsulating comprises forming a glob-top encapsulant.